Method of and apparatus for reducing current of semiconductor memory device
US4933902A · kind A · utility
25Cited by
7References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1988 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | Jul 22, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit of a dynamic random access memory (RAM) comprises a power-on reset circuit and an NOR gate conneced to a row address strobe (RAS) terminal and the reset circuit. In operation, the power-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level row address strobe (RAS) signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic random access memory (RAM) at the time of turning on the power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.