Method for improving the page hit ratio of a page mode main memory system
US4933910A · kind A · utility
70Cited by
4References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 6, 1988 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | Jul 6, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Page mode memory access is enabled despite an immediately previous idle cycle. A row address strobe signal is maintained active during an idle cycle so that if a page hit is detected on a subsequent memory cycle, all that is needed to read or write to memory is a column address strobe signal which can be provided via a page mode access. In this manner, memory speed is enhanced because a conventional access is not required on the first memory cycle following one or more idle cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.