Buffer queue write pointer control circuit notably for self-channelling packet time-division switching system
US4933932A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1988 |
| Grant date | Jun 12, 1990 |
| Priority date | — |
| Expiry date | Dec 21, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/255
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The circuit embodying the invention comprises a pointer memory memorizing J=16 decremented write pointers associated with J=16 buffer queues. A channelling word supplied conjointly to incoming data and indicating the buffer queue in which this data is to be written, addresses the corresponding decremented write pointer. The write pointer and the channelling word form a write address for a buffer memory used as a medium for the J=16 queues. A comparator detects equality between the write pointer and the read pointer and in this case inhibits the acceptance of the incoming data which would overlay data not yet read. Logic means associated with the comparator control the updating, by possible incrementation, of the write pointer values contained in the pointer memory, after each data read in the buffer queues. This circuit is particularly well suited for use in an asynchronous self-channelling packet time-division switching system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.