Thin film transistor array
US4935792A · kind A · utility
51Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1988 |
| Grant date | Jun 19, 1990 |
| Priority date | — |
| Expiry date | Nov 1, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor array in which a plurality of thin film transistors arranged in the shape of an array on a substrate each transistor includes a gate electrode, a first insulating layer, a semiconducting layer, a second insulating layer, a source electrode and a drain electrode stacked sequentially one on another such that the first insulating layer and the second insulating layer are interposed at an overlap portion between a gate bus bar for connecting the gate electrodes in common and a source bus bar for connecting the source electrodes in common.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.