Device for minimizing parasitic junction capacitances in an insulated collector vertical P-N-P transistor
US4935796A · kind A · utility
2Cited by
10References
6Claims
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Assignee
Inventors
Key dates
| Filing date | Feb 8, 1988 |
| Grant date | Jun 19, 1990 |
| Priority date | — |
| Expiry date | Feb 8, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for minimizing parasitic junction capacitances in an isolated collector vertical PNP transistor, having a terminal N connected to an epitaxial n layer, comprises a bootstrap circuit including an emitter follower vertical PNP transistor having its emitter and base respectively connected to the terminal of the epitaxial n layer and the collector of the isolated collector transistor; further, a bias resistance is connected between the emitter and one pole of a voltage supply to the emitter follower.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.