Multiple port bus interface controller with slave bus
US4935868A · kind A · utility
48Cited by
12References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 28, 1988 |
| Grant date | Jun 19, 1990 |
| Priority date | — |
| Expiry date | Nov 28, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.