Semiconductor memory device having three-transistor type memory cells structure without additional gates
US4935896A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 1988 |
| Grant date | Jun 19, 1990 |
| Priority date | — |
| Expiry date | Nov 2, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.