Low power, high noise margin logic gates employing enhancement mode switching FETs
US4937474A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1989 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Feb 23, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0952
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low power, high noise margin logic gate comprises: an input terminal, an output terminal, and first and second voltage supply terminals; an enhancement mode switching FET having a gate connected to the input terminal, a source and a drain; a load device connected between the drain of the switching FET and the first voltage supply terminal; a feedback device connected between the source of the switching FET and the second voltage supply terminal; a two terminal level shift device connected between the drain of the switching FET and the output terminal; and an enhancement mode pulldown FET having a gate connected to the source of the switching FET, a source connected to the second voltage supply terminal, and a drain connected to the output terminal. The logic gate as defined above operates as an invertor. The logic gate may further comprise one or more additional enhancement mode switching FETs, each having a drain connected to the load device, a source connected to the feedback device, and a gate connected to a corresponding input terminal. With the additional switching FETs and input terminals, the logic gate functions as a NOR gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.