Dither circuit responsive to zero input signal level
US4937576A · kind A · utility
25Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1989 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Nov 22, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dither circuit including an adder for receiving an input signal and a dither signal which is generated by a dither signal generator, a level detection circuit for detecting the signal level of the input signal, and a dither control circuit for stopping the feeding of the dither signal to the adder when the level detection circuit detects that the signal level of the input signal is zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.