Semiconductor integrated circuit chip-to-chip interconnection scheme
US4937653A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1988 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Jul 21, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit chip-to-chip interconnections are made via gold pads on each chip that are bonded to corresponding gold pads on a silicon wafer chip carrier. The pads on the chips and/or the pads on the carrier are characterized by texturing (roughening) with a feature size of the order of a micrometer or less, so that each of the pads on the chip can be attached to each of the pads on the carrier by compression bonding at room temperature--i.e., cold-well bonding. In particular, the texturing of the gold pads on the silicon carrier is obtained by etching V-grooves locally on the surface of the underlying silicon carrier in the regions of the pads, thermally growing a silicon dioxide layer on the silicon carrier, and depositing the gold on the silicon dioxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.