High speed bus with virtual memory data transfer and rerun cycle capability
US4937734A · kind A · utility
119Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1989 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Jun 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed data transfer bus with virtual memory capability. The bus has particular applications in computer systems which employ peripheral devices. The bus allows high speed data transfer through the use of a virtual memory scheme. This minimizes the number of lines required to implement the bus and minimizes the amount of time a particular device is required to wait before it can access the bus and complete a data transfer. Control signals are employed that are driven both active and inactive, facilitating interfacing the bus to low-power CMOS technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.