Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction
US4937738A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 23, 1985 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Aug 23, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory contained in a processor features a high efficiency in spite of its small capacity. In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory. By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.