High performance dynamic ram interface
US4937791A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1988 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Jun 2, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and associated apparatus for accessing a plurality of DRAMs in the static column mode by a high performance instruction processor to provide minimum wait state accessing thereby. The method comprises the steps of, having the instruction processor emit each instruction address as an address containing a bank number field, a row address field, and column address field; providing a table for storing a set of open pages being the current row address for each bank where a bank is associated with a respective one of the plurality DRAMs; for each instruction address emitted from the instruction processor, determining whether there is a match between the row address stored in the table and the row address emitted from the instruction processor employing the bank number as an index into the table of open pages; if the two addresses match, continuing the memory access to the indicated bank in a continuing static column mode; and, if the two addresses do not match, overwriting the old address for the indicated bank in the table with the new row address and continuing the memory access by beginning a new static column mode access to the indicated bank. In the preferred embodiment, the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.