Loop status verification system
US4937851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1989 |
| Grant date | Jun 26, 1990 |
| Priority date | — |
| Expiry date | Apr 28, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M11/04
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A system is disclosed for verifying the integrity of each one of a number of communication paths, illustratively telephone subscriber loops, that runs between a near end location, illustratively a telephone company central office, and a corresponding remote ("far end") location(s). This system utilizes circuitry, such as a line verification module, that is located at the far end of each path to impart a selected test signal specifically a selected one of a number of sub-audible frequencies, thereto. In one embodiment, the circuitry continously transmits a test signal over the path. The level of the test signal is automatically adjusted such that this signal remains at an approximately constant amplitude regardless of whether that path is in an on-hook or off-hook condition. Central office monitoring circuitry is connected to the near end of every path being verified. For each such path, the monitoring circuitry first "learns" the frequency associated with the test signal appearing over that path, and thereafter detects a cessation or unexpected change in the test signal occurring at the near end thereof that is indicative of a possible loss of path (e.g. loop) integrity and, in tur…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.