Process for fabricating isolated vertical bipolar and JFET transistors
US4939099A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1989 |
| Grant date | Jul 3, 1990 |
| Priority date | — |
| Expiry date | Sep 21, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/673
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction isolation is completed by the doping and diffusion of shallow junction isolation regions (46, 122) at the same time that deep collector regions (48) are formed. A JFET source region (74) and a drain region (76) are formed simultaneously with a VPNP emitter region (70). A JFET gate contact region (88) is formed simultaenously with a VPNP base contact region (84), a VPNP buried region contact (86) and optionally with the doping of a capacitor electrode (124).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.