Process for the production of a MIS transistor with a raised substrate/gate dielectric interface end

US4939100A · kind A · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Pierre Jeuch · Chauny, FR
• Jean-Jacques Niez · Grenoble, FR

Key dates

• Filing date: Dec 15, 1988
• Grant date: Jul 3, 1990
• Expiry date: Dec 15, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/027

Abstract

A process for the production of a MIS transistor with a rising substrate/gate dielectric interface wall wherein on the surface of a semiconductor substrate having a given doping type is formed a first electrically insulating layer surrounding a zone of the substrate surface. On the first insulating layer and on said zone is formed a second layer. Part of that zone is made to appear by eliminating a fragment of the second layer, which fragment extends above that part, which thus constitutes the bottom of a hole made in the second layer and above part of the first insulating layer. A cavity is formed having at least one rising wall in the bottom of the hole. A third electrically insulating layer is formed on the surface of the aforesaid zone part. On the thus treated surface is formed an electrically conductive layer which eliminated, except in a zone corresponding to the fragment, so as to obtain a transistor gate. The remainder of the second layer is eliminated and the transistor source and drain zones are formed, the drain zone being located on the side of the rising wall.