Semiconductor switch with parallel DMOS and IGT
US4939566A · kind A · utility
43Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1987 |
| Grant date | Jul 3, 1990 |
| Priority date | — |
| Expiry date | Oct 30, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor switch comprising a lateral DMOS and a lateral IGT both of which can be fabricated in a monolithic integrated circuit. In operation the lateral DMOS stays on while the lateral IGT is switched off in order to reduce turn off power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.