Three-dimensional integrated circuit and manufacturing method thereof
US4939568A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1989 |
| Grant date | Jul 3, 1990 |
| Priority date | — |
| Expiry date | Mar 17, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to a three-dimensional stacked IC and a method for forming a three-dimensional stacked IC on a base plate. The three-dimensional stacked IC includes a unit semiconductor IC, which has constituent ICs formed on either one surface or on both surfaces of a substrate. In addition, the unit semiconductor ICs have a plurality of conducting posts buried in and penetrating through the substrate and insulated therefrom. The unit semiconductor ICs have interconnection terminals provided on both sides of the substrate for connecting other unit semiconductor ICs or a base plate. By stacking plural unit ICs on the base plate, a very large scale IC can be fabricated. Each constituent IC is formed on a bulk silicon substrate, therefore excellent quality can be obtained. This can be also applied to the fabrication of a ROM structure such as a PROM or MASK ROM, using single unit semiconductor ICs, wherein a wiring for the ROM can be formed on the second surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.