Interlock circuit for preventing corruption of telephone line signals
US4939765A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1989 |
| Grant date | Jul 3, 1990 |
| Priority date | — |
| Expiry date | Nov 24, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q1/442
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Corruption of communication signals on a telephone line by the direct (low impedance) interfacing of test equiupment to the line is precluded by a protective interlock circuit, which prevents the test set from seizing the line if data traffic is present. The interlock circuit is coupled between the line circuit to be accessed and the test equipment, and includes a multiple band frequency detector, which monitors the line for signals lying within (in and out-of-audio) frequency bands. Should the detector identify any traffic within its sensitivity range (out of the audio band) during the interval of a timing pulse produced by the closure of a switch, the logic level applied to combinational logic will change state and prevent the generation of a test set enabling signal. The test set enabling signal is normally coupled to a `line-seize` transistor circuit within the test set, so that, without this enabling signal, the test set is effectively locked-out from the line and data cannot be corrupted. Should the frequency detector not have produced an out of audio band detection signal after the expiration of the timing pulse, the combinational logic circuit and an associated flip-flop ge…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.