Configuration control circuit for programmable logic devices
US4940909A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1989 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | May 12, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A configuration control circuit in an integrated circuit device, such as a programmable logic device, having a programmable memory for storing configuration bits and one or more shift registers which are loadable from the memory. The memory is an array of nonvolatile memory cells that can be user programmed with data corresponding to a desired device architecture. The shift registers are loaded with this data upon power up or a reset. The registers in combination with other circuit gates control the operation of the device such that a particular architecture is implemented. The various configurations can be tested without altering the contents of the memory by loading the shift register externally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.