Temperature compensated monolithic delay circuit
US4940910A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 1989 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Jun 2, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/907
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.