Combined rate/width modulation arrangement
US4940979A · kind A · utility
2Cited by
3References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1988 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Apr 26, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/86
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Pulse modulation circuitry which receives n binary data bits and generates a rate/width pulse modulated signal representing the binary value of the received data bits. The lower order m of the n bits generate a rate modulated signal having a number of pulses equal to the binary value of the m bits. The remainder of the n bits width modulate the rate modulated pulses. Each least significant bit increase in the binary value of the received date bits increases the width of a rate modulated pulse by a predetermined amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.