Structure for protecting thin dielectrics during processing
US4941028A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1988 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Aug 10, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure used to protect a dielectric is disclosed wherein a transistor located nearby the dielectric is connected in series with a conductor overlying the fragile dielectric such that the transistor gate will accumulate charge along with the conductive material over the fragile dielectric. After fabrication and during normal circuit operation, this transistor device remains in an off state, isolating the fragile dielectric node from other circuitry. In an alternate embodiment the protection transistor is a floating gate depletion device, which would always be on until the circuit is activated. At the time the circuit is activated, the device is turned off by trapping electrons on the gate by avalancing a junction associated with it. In a preferred, embodiment, a buried contact is formed after the conductor overlying the dielectric, usually polysilicon, is formed. This buried contact connects the conductor to the discharging transistor. Alternatively, a weak portion in the dielectric may be deliberately created by placing a lightly doped N-type diffusion in the area under which the buried contact is desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.