Time division switching for multi-channel calls using two time switch memories acting as a frame aligner
US4941141A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1988 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Dec 29, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/08
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Signals on an incoming highway of a time division switching system are written into an alternate one of first and second time switch memories and are sequentially read out of the other alternate one of the memories into the time slots of an outgoing highway of the system in accordance with a phase difference between incoming and outgoing frames and a time slot interchanging relationship between signals on the incoming highway and corresponding signals on the outgoing highway, so that the beginning of the outgoing frame coincides with one of the time slots of the incoming frame which is displaced from the beginning of the incoming frame by an amount equal to the detected phase difference. Alternatively, if the time slot of at least one signal of a multi-channel call on the incoming highway is later than the time slot of a corresponding signal on the outgoing highway, all signals of that multi-channel call are sequentially read out of the memories into a given outgoing highway so that they correspond to those on an incoming frame which is one frame prior to the one being written at the beginning of the given outgoing frame. If the time slots of all signals of a multi-channel call on …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.