Linear jitter attenuator
US4941156A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1989 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Mar 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/061
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A jitter attenuation circuit includes a FIFO data register (10) which is operable to receive data that is synchronized with a Write clock output therefrom synchronized with a Read clock. The data is written to the FIFO register (10) from a location determined by a Write pointer (12). The data is read out from the FIFO register (10) from a location determined by a Read pointer (14) which is clocked by a Read clock. The Read clock is synchronized with the Write clock by a phase lock loop (24). The phase lock loop (24) has a phase detector (26) which is operable to accrue phase error over intervals of 2.pi. radians such that the phase lock loop (24) virtually never loses lock as a result of phase jitter on the Write clock. The phase lock loop (24) has contained therein a digitally controlled linear oscillator (28) wherein the phase detector (26) provides a quantized output to incrementally step the digitally controlled oscillator (28) up or down in frequency to track the Write clock while attenuating jitter thereon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.