Frequency multiplier circuitry and method
US4941160A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 1989 |
| Grant date | Jul 10, 1990 |
| Priority date | — |
| Expiry date | Mar 31, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generally there is provided circuitry and a method for frequency multiplication of a first signal source including a first counter for counting pulses from a second signal of higher frequency by counting from a loaded value and generating a circuit output each time the first counter resets. A second counter is used to count cycles of the first counter and generate a feedback signal when a predetermined number of cycles have been completed (the system multiplication factor). Calibration is achieved by comparing the end of the period of the first signal to the occurrence of a feedback signal. In response the comparision circuit causes the loaded value to be changed to thereby control the output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.