Elimination of linearity superposition error in digital-to-analog converters
US4942397A · kind A · utility
7Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1988 |
| Grant date | Jul 17, 1990 |
| Priority date | — |
| Expiry date | Jul 26, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A converter, of the type having an R-2R resistive network and switches, is used to convert a digital signal of n-bits into an analog signal. A plurality of first interconnectors is used to electrically connect a first switch input of one of the switches to a first voltage reference node by separately extending directly therebetween. A plurality of second interconnectors is used to electrically connect a second switch input on the same one of the switches to a second voltage reference node is a similar fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.