Error connection device for parity protected memory systems
US4942575A · kind A · utility
17Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1988 |
| Grant date | Jul 17, 1990 |
| Priority date | — |
| Expiry date | Jun 17, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The use of a redundant memory subsystem, memory flow control, and a method of copying (srubbing) data from the location of one memory subsystem to the corresponding location in the other memory subsystem provides correction of soft errors in a parity protected memory system without degrading the performance of the memory system except when an error occurs. A copy of the correct data is also provided to the memory system when a location in either of the memory subsystems experiences a hard error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.