Circuit for dividing the frequency of a digital clock signal by two and one-half
US4942595A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 1988 |
| Grant date | Jul 17, 1990 |
| Priority date | — |
| Expiry date | Dec 5, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for dividing a clock signal by two and one-half (2.5) is shown. The divide by two and one-half (2.5) circuit includes a clock selector circuit arranged to output a selected polarity of the first clock signal. A ring counter arranged to receive the clock selector circuit output signal, and output a signal that has a period of 3 times (3.times.) the signal received from the clock selector circuit. A divide by two circuit connected to the ring counter circuit and to the clock selector circuit. The divide by two circuit divides the ring counter output signal by two to produce an output signal. The divide by two output signal is then fed back to the clock selector circuit to regulate the selection of the first clock signal polarity, causing the ring counter to output a clock signal with a period of two and one-half times (2.5.times.) the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.