Process for manufacturing a dynamic random access memory cell
US4945066A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1988 |
| Grant date | Jul 31, 1990 |
| Priority date | — |
| Expiry date | Feb 23, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/30
Abstract
A process for manufacturing a dynamic random access memory (DRAM) cell wherein an improvement is made in an occurrence of soft errors in operation of a memory device, said soft errors resulting from alpha particles being produced from uranium-series materials included in fabricating materials during fabrication of memory chips, especially in the package of the chip. In a single transistor memory cell, through forming boron layers below a storage capacitor region and below a drain region of the transistor coupled with a bit line, a barrier is formed against the minority carriers resulting from the alpha particles within the substrate. Also, through enlarging the storage capacitor region toward a field oxide layer just around the capacitor perimeter, a capacitance of the storage capacitor is increased so that the influence of the soft errors is negligible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.