Level and edge sensitive input circuit
US4945261A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1989 |
| Grant date | Jul 31, 1990 |
| Priority date | — |
| Expiry date | Mar 27, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R19/16557
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A level and edge sensitive input circuit can recognize a variety of types of input signals on an input line and provide a standard digital logic output for use within the equipment. The input circuit is formed from a bias circuit, two comparators, and a memory bit. The bias circuit applies a bias voltage to the input line. A first comparator inverts the state of the memory bit when the input signals are an increment above the bias voltage. The second comparator clears the state of the memory bit when the input signals are an increment below the bias voltage. In this way, the memory bit cycles through states which provide the desired output signals for use within the equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.