Dummy/trim DAC for capacitor digital-to-analog converter
US4947169A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1989 |
| Grant date | Aug 7, 1990 |
| Priority date | — |
| Expiry date | Oct 24, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a successive approximation analog-to-digital converter having a main CDAC and a trim CDAC includes resistors in the main CDAC connected in series with various bit switch FETs. The resistors are precisely matched to equivalent resistances of trimmable voltage divider circuits connected in series with various corresponding bit switch FETs in the trim DAC, to prevent non-linear parasitic capactiance and voltage-current properties of first and second clamping FETs from "unbalancing" the voltages on the charge summing conductors of the main DAC and the trim DAC during turn-off of the first and second clamping FETs after they have been turned on to equalize the voltages of the charge summing conductors. In another embodiment, separate trim and dummy DACs are provided to improve the accuracy to which the resistances in the main CDAC and trim CDAC can, as a practical matter, be matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.