Arbitral dynamic cache using processor storage
US4947319A · kind A · utility
41Cited by
7References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1988 |
| Grant date | Aug 7, 1990 |
| Priority date | — |
| Expiry date | Sep 15, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data cache in a computer operating system that dynamically adapts its size in response to competing demands for processor storage, and exploits the storage cooperatively with other operating system components. An arbiter is used to determine the appropriate size of the cache based upon competing demands for memory. The arbiter is entered cyclically and samples user's wait states. The arbiter then makes a decision to decrease or increase the size of the cache in accordance with predetermined parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.