Pipelined processor for implementing the least-mean-squares algorithm
US4947363A · kind A · utility
12Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 12, 1988 |
| Grant date | Aug 7, 1990 |
| Priority date | — |
| Expiry date | Dec 12, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H21/0012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A filter processor implements the least mean squares (LMS) algorithm in an N tap digital filter in (N+1) time cycles, where N is an integer. A filter structure is shown which is implemented with a processor having an update portion and a convolution portion. A single memory is shared between the two portions, and the same data is concurrently coupled to both portions for concurrent use. The filter may be efficiently pipelined wherein successive adaptive and convolution operations are executed to efficiently implement an N tap filter with a minimum amount of circuity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.