Method in a computing system for performing a multiplication
US4947364A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 1989 |
| Grant date | Aug 7, 1990 |
| Priority date | — |
| Expiry date | Aug 9, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5332
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit. Second, for every other bit in the current section that is a "1", a shift-and-add operation is performed by shifting, via the preshifter, the contents of the first register by an amount equa…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.