Method of manufacturing self-aligned conformal metallization of semiconductor wafer by selective metal deposition
US4948755A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1989 |
| Grant date | Aug 14, 1990 |
| Priority date | — |
| Expiry date | Jul 11, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/97
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for fabricating a semiconductor integrated circuit which includes the selective deposition of a metal, such as tungsten, into a contact opening formed in a dielectric layer, followed by the deposition of a thin silicon layer over the dielectric and metal-filled opening and the deposition of a second dielectric layer over the thin silicon layer. An opening or trench is formed in the upper second dielectric layer using the silicon as an etch stop, and a metal such as tungsten is selectively deposited to fill the trench wherever the exposed silicon is present. In one embodiment of the invention, prior to the filling of the trench, the exposed silicon is reacted with a blanket layer of a metal to form a metal silicide layer at the lower surface of the trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.