Transistor construction for low noise output driver
US4949139A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1988 |
| Grant date | Aug 14, 1990 |
| Priority date | — |
| Expiry date | Sep 9, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D44/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.