EEPROM cell with integral select transistor
US4949140A · kind A · utility
32Cited by
11References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1989 |
| Grant date | Aug 14, 1990 |
| Priority date | — |
| Expiry date | Apr 12, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
An electrically programmable and electrically erasable floating gate memory device which includes an integrally formed select device. In the n-channel embodiment, a boron region is formed adjacent to the drain region under the control gate and extends slightly under the floating gate. This region is formed using a spacer defined with an anisotropic etching step. The region, in addition to providing enhanced programming, prevents conduction when over-erasing has occurred, that is, when the erasing causes the cell to be depletion-like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.