Erasable read-only semiconductor memory device
US4949305A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1988 |
| Grant date | Aug 14, 1990 |
| Priority date | — |
| Expiry date | Oct 6, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory transistors are arranged in a plurality of rows and a plurality of columns. A source line is formed for every two bit lines formed in the column direction, each connected to the memory transistors of one column. A source region of each memory transistor is connected, on one side, to a source line adjacent thereto and, on the other side, to a source line through the source region of the adjacent memory transistor, through impurity regions respectively. A floating gate is formed to extend to a position under the corresponding source line. In another example, a source line is formed for each bit line formed in the column direction. The source region of each memory transistor is connected to the adjacent source lines on both sides thereof through impurity regions. The floating gate is formed to extend to positions under both adjacent source lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.