Parallel computer with distributed shared memories and distributed task activating circuits
US4951193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1987 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Aug 14, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/484
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.