Direct digital synthesizer with selectably randomized accumulator
US4951237A · kind A · utility
27Cited by
4References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 22, 1988 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Apr 22, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/902
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A direct digital synthesizer (DDS) accumulator circuit is disclosed wherein a selected few of the low order accumulator bits are dithered by a pseudorandom number generator in order to introduce flat frequency deviation density to suppress spurious signals including those close-in to the output or fundamental frequency. The accumulator circuit may advantageously be sectioned into a lower order accumulator and higher order accumulator in a pipelined combination with a sine approximation output circuit in order to construct a DDS circuit wherein such spur suppression is achieved without decreasing system throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.