Digital memory system
US4951252A · kind A · utility
7Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 1988 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Oct 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital memory system of the type which includes an amplifier transistor connected to provide an amplified bit line signal corresponding to the state of a selected memory cell. A bit line pull-up transistor is positioned to function as a bit line current source and as a load device for the amplifier transistor. The amplifier transistor is connected between the pull-up transistor and the bit line and an output node positioned between the pull-up and amplifier transistors provides the amplified bit line signal corresponding to the state of a selected memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.