Static memory unit having a plurality of test modes, and computer equipped with such units
US4951254A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 1988 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Nov 16, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/46
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.