High speed digital programmable frequency divider
US4951303A · kind A · utility
Inventor
Key dates
| Filing date | Oct 31, 1988 |
| Grant date | Aug 21, 1990 |
| Priority date | — |
| Expiry date | Oct 31, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/667
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.