Integrated logic circuit with instability damping
US4952822A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 10, 1988 |
| Grant date | Aug 28, 1990 |
| Priority date | — |
| Expiry date | Nov 10, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In integrated logic circuits, at least one additional transistor may be provided in cascode connection with at least one other component in order to avoid detrimentally high electrical fields in components of such circuits. The control electrode is then connected to one of the power supply lines. When the state of the logic circuit changes, switching currents generate voltage peaks on the power supply lines due to the inductance of these lines. Via the chip capacitance these voltage peaks jump from one power supply line to the other. Thus, a positive feedback loop is formed which comprises one power supply line, the chip capacitance, the other power supply line and the additional transistor. Instabilities in such circuits are damped by inserting a resistance element between the control electrode of the additional transistor and the power supply line coupled thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.