Patent · US Expired

Circuit arrangement for controlling the load current in a power MOSFET

US4952827A · kind A · utility

17Cited by

8References

3Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Ludwig Leipold · Munich, DE
Rainald Sander · Oberhaching, DE
Jenoe Tihanyi · Tauberbischofsheim, DE
Roland Weber · Munich, DE

Key dates

Filing date	Nov 15, 1989
Grant date	Aug 28, 1990
Priority date	—
Expiry date	Nov 15, 2009

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/063
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A circuit arrangement for controlling load current of a power MOSFET wherein the load is connected at the source terminal includes a second FET having a defined threshold voltage connected with its drain-source path inserted between the gate and source of the power MOSFET. A third FET connects the gate terminal of the second FET to the drain voltage of the power MOSFET when the power MOSFET is in the conductive condition. When the drain-source voltage of the power MOSFET becomes higher than the threshold voltage of the second FET, the second FET becomes conductive and drives the gate-source voltage of the power MOSFET down.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.