MOS stage with high output resistance particularly for integrated circuits
US4952885A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 1989 |
| Grant date | Aug 28, 1990 |
| Priority date | — |
| Expiry date | Feb 15, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/345
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.