Selective clearing of latched circuits
US4952926A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 29, 1988 |
| Grant date | Aug 28, 1990 |
| Priority date | — |
| Expiry date | Apr 29, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG08B26/002
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An alarm system includes a controller and a plurality of transponders having different addresses. Certain of the transponders include switch means for monitoring conditions, and latch circuits to retain memory of the switch conditions. The controller includes means for positive recognition of a latched alarm or trouble condition in any transponder, before the clear-alarm signal or clear-trouble signal is sent from the controller to restore the alarm circuits to their original states. This insures that an alarm or trouble condition at a transponder is not "missed" by inadvertent clearing before a positive recognition is registered in the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.