Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US4953073A · kind A · utility
92Cited by
12References
2Claims
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Assignee
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Key dates
| Filing date | Feb 6, 1986 |
| Grant date | Aug 28, 1990 |
| Priority date | — |
| Expiry date | Feb 6, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.