Data bus enable verification logic
US4953167A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 1988 |
| Grant date | Aug 28, 1990 |
| Priority date | — |
| Expiry date | Sep 13, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.